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HD66350T (tft driver) 256-level grayscale tft for xga/sxga/uxga systems ade-207-297(z) preliminary rev.0.6 december 1998 description the HD66350T is a tft-lcd source driver lsi suitable for xga, sxga, and uxga systems. it receives 8-bit-per-pixel digital display data, and generates and outputs voltages for 256 grayscales. the output circuit includes an operational amplifier, and is capable of alternate output of 256 positive- polarity grayscale voltages and 256 negative-polarity grayscale voltages on individual output pins (dot inversion drive). users can select 384 or 402 outputs. for xga and sxga, respectively, eight and ten 384-output lsis are used. for uxga, twelve 402-output lsis are used. features high-speed operation ? operating clock: 65 mhz (vcc = 3.0 to 3.6 v) and 50 mhz (vcc = 2.5 to 3.0 v) operational power-supply voltage range ? v cc = 2.5 to 3.6 v ? v lcd = 10 to 15.5 v lcd drive voltage ? low-voltage side: 0.1 to v lcd /2 ?0.2 (v) ? high-voltage side: v lcd /2 + 0.2 to v lcd ?0.1 (v) lcd drive outputs ? 384/402 outputs can be selected: eight 384-output lsis for xga, ten 384-output lsis for sxga, and twelve 402-output lsis for uxga data inversion function ? each port has a data inversion pin (a total of two pins), which reduces the power consumption of the data buses.
HD66350T 2 multicolor display ? the HD66350T receives 8-bit-per-pixel digital display data, and selects and outputs a display voltage from 256 grayscale voltages, enabling a maximum of 16,770,000 display colors (full colors) when using r/g/b color filters. 48 data bits (8 grayscale code bits rgb 2 ports) high-voltage asymmetric drive ? the wide dynamic range of 15.3 v and the ability to output positive-polarity and negative- polarity voltages make it unnecessary to provide a counter-electrode alternating current. also, since both positive-polarity and negative-polarity voltages are generated by an externally provided reference power supply, gamma compensation is possible according to the characteristics of the liquid crystal. dot inversion drive ? the voltage can be alternated between positive polarity and negative polarity on individual output pins, allowing a dot-by-dot inversion drive even with a single-sided layout configuration. this provides a high-quality display with little crosstalk. low-output voltage deviation of 3 mv operational amplifier ? the output circuit includes an operational amplifier. bidirectional shift package ? tcp (customized package dimensions) supported systems ? xga (1024 768 dots), sxga (1280 1024 dots), and uxga (1600 1200 dots) applications ? portable pcs and monitors
HD66350T 3 pin arrangement y402 y401 y400 y399 y398 y397 y396 y395 y394 y9 y8 y7 y6 y5 y4 y3 y2 y1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 eio2 d57 d56 d55 d54 d53 d52 d51 d50 d47 d46 d45 d44 d43 d42 d41 d40 d37 d36 d35 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 d34 d33 d32 d31 d30 vcc os shl fsl stpls odd/evn v9 v8 v7 v6 v5 v lcd agnd v4 v3 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 v2 v1 v0 gnd test2 test cl2 cl1 m pol1 pol2 d27 d26 d25 d24 d23 d22 d21 d20 d17 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 d16 d15 d14 d13 d12 d11 d10 d07 d06 d05 d04 d03 d02 d01 d00 eio1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 y384 y383 y382 y381 y380 y379 y378 y377 y376 y9 y8 y7 y6 y5 y4 y3 y2 y1 top view the tcp package dimensions are not standardized. ?384-output lsi ?402-output lsi 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 top view figure 1 pin arrangement
HD66350T 4 internal block diagram cl2 eio1 eio2 pol1 pol2 cl1 shl os m d27 to d20, d17 to d10, d07 to d00 v lcd v cc gnd v0, v1, v2, v3, v4 v5, v6, v7, v8, v9 clock control negative-polarity grayscale voltage latch address selector 384/402 latch circuits (1) 8 planes 384/402 latch circuits (2) 8 planes grayscale voltage generation positive-polarity grayscale voltage data inversion circuit 384/402 decoders 384/402 output amplifier circuits y1y2y3y4 y402 y384 fsl stpls odd/evn test test2 figure 2 block diagram 1. clock control unit generates the chip-enable signals (eio2, eio1) and controls internal timing signals. 2. data inversion circuit uses the pol1 and pol2 signals to perform data polarity inversion (pol = 1) or non-inversion (pol = 0) processing of input display data. 3. latch address selector generates latch signals for sequentially latching the input display data. setting the os pin enables the operation of the 384-output driver (os = 0) or 402-output driver (os = 1). 4. latch circuits (1) 402 8-bit latch circuits that sequentially latch 6-output 8-bit input display data. 5. latch circuits (2) perform latching, in synchronization with cl1, of the 402 8-bit data latched by latch circuits (1).
HD66350T 5 6. decoders decode the 8-bit data and select the liquid-crystal application voltages. 7. grayscale voltage generation unit performs resistance- and capacitance-division of the external input voltage, and generates 256 positive-polarity grayscales and 256 negative-polarity grayscales. 8. output amplifier circuits output the grayscale voltage that has been selected for each output and buffered in the operational amplifier.
HD66350T 6 pin functions table 1 pin functions signal name quantity input/output function v lcd 1 power supply + + v lcd ?gnd: driver-circuit power supply v cc ?gnd: logic-circuit power supply gnd v cc v lcd v cc 1 power supply gnd/agnd 2 power supply v9 to v5 5 power supply reference power supply for generating the liquid-crystal application voltage. supplies a voltage in the range vlcd/2 + 0.5 to vlcd ?0.1 v to pins v0?4, and a voltage in the range 0.1 v to vlcd/2 ?0.5 to pins v5?9. v4 to v0 5 cl1 1 input data of one line is transferred to the latch at the rising edge of this clock, and the liquid-crystal application voltage is output at the falling edge. one pulse must be input in each horizontal period. cl2 1 input display data is latched at the rising edge of this clock. for the 384-output lsis, after the start pulse input, the start pulse output goes high at the rising edge of the 63rd (66th) clock, and this becomes the start pulse of the next-stage driver. the 65th (68th) clock of the first-stage driver is the start-pulse latch clock of the next-stage driver. after the start pulse input, display data latching is halted automatically when 66 (69) clock pulses are input. (values in parentheses are for the 402-output lsis.) pol1, pol2 1 input data-polarity inversion signal to reduce power consumption of data bus lines in the interface. when pol1 or pol2 is high, display data is inverted in the driver. when pol1 or pol2 is low, display data is input without inversion in the driver. the pol1 signal controls the polarity of 24 data (d00 to d27). the pol2 signal controls the polarity of 24 data (d30 to d57). when pol1 or pol2 is not used, this pin must be either high or low. d57 to d50, 48 input inputs 8-bit (grayscale data) 6-pixel display data. d47 to d40, dx0 is the lsb, and dx7 is the msb. d37 to d30, d27 to d20, d17 to d10, d07 to d00
HD66350T 7 table 1 pin functions (cont) signal name quantity input/output function eio1, eio2 2 input/output chip-enable signals. input/output switching is controlled by the shl signal. when these signals are used as inputs, display data latching is performed when the input goes high. when these signals are used as outputs, a low-to-high transition is made at the rising edge of the 63rd (66th) clock of the cl2 signal, and the next-stage driver is activated. (values in parentheses are for the 402-output lsis.) eio2 output input eio1 input output shl v cc gnd m 1 input current-alternating signal, controlling the liquid-crystal alternating-current drive. the m signal is input after provision of a setup time with respect to the rise of the cl1 signal. positive-polarity (v0?4) and negative-polarity (v5 v9) output voltages are generated as shown below according to the polarity of the latched m signal. even output pins (y2,y4, . ..,y384) odd output pins (y1,y3, . ..,y383) m negative-polarity liquid-crystal application voltage is output positive-polarity liquid-crystal application voltage is output positive-polarity liquid-crystal application voltage is output negative-polarity liquid-crystal application voltage is output 0 1 os 1 input pin for switching the number of outputs. when os is low, this lsi operates as a 384-output product. when os is high, this lsi operates as a 402-output product. since this pin performs 50-k w pull-down processing within the chip, it must be opened or low when used as the 384- output product. when this pin is used as the 402-output product, it must be high. fsl 1 input pin for switching the operating speed. when it is used in the range of 40 to 65 mhz, input high level. when it is used in the range of 30 to 40 mhz, input low level. since this pin performs 50-k w pull-down processing within the chip, it can be opened when it is used in the range of 30 to 40 mhz. stpls 1 input input the same signal as the start pulse, which is input in the first-stage ic, to the stpls pin in all drivers. this pin is required for high-speed operation. odd/evn 1 input when this pin is used for 402-output operation (os = high), use the first, third, or fifth pin as low level in the order of fetched data. use the second, fourth, or sixth pin as high level. this pin is required for 402-output operation. when this pin is used for 384-output operation (os = low), set this pin to low in all drivers. since this pin performs 50- k w pull-down processing within the chip, it can be opened.
HD66350T 8 table 1 pin functions (cont) signal name quantity input/output function y1 to y402 402 output signal lines for output of liquid-crystal application voltages. for the 384-output lsi, 18 invalid outputs can be selected to not lead to the tcp. test, test2 2 input test pins. set these pins to low. since these pins perform 50-k w pull-down processing within the chip, use them opened or low. shl 1 input controls display-data shift direction. ?384-output lsi (os is low or opened). last 1st v cc 1st last gnd d57 to d50 d47 to d40 d37 to d30 d27 to d20 d17 to d10 d07 to d00 d57 to d50 d47 to d40 d37 to d30 d27 to d20 d17 to d10 d07 to d00 d57 to d50 d47 to d40 d37 to d30 d27 to d20 d17 to d10 d07 to d00 y384 y383 y382 y381 y380 y379 y6 y5 y4 y3 y2 y1 d57 to d50 d47 to d40 d37 to d30 d27 to d20 d17 to d10 d07 to d00 d57 to d50 d47 to d40 d37 to d30 d27 to d20 d17 to d10 d07 to d00 y384 y383 y382 y381 y380 y379 y6 y5 y4 y3 y2 y1 d57 to d50 d47 to d40 d37 to d30 d27 to d20 d17 to d10 d07 to d00
HD66350T 9 table 1 pin functions (cont) signal name quantity input/output function shl 1 input ?402-output lsi (os is high). last 1st v cc 1st last gnd d57 to d50 d47 to d40 d37 to d30 d27 to d20 d17 to d10 d07 to d00 d57 to d50 d47 to d40 d37 to d30 d27 to d20 d17 to d10 d07 to d00 d57 to d50 d47 to d40 d37 to d30 d27 to d20 d17 to d10 d07 to d00 y402 y401 y400 y399 y398 y397 y6 y5 y4 y3 y2 y1 d57 to d50 d47 to d40 d37 to d30 d27 to d20 d17 to d10 d07 to d00 d57 to d50 d47 to d40 d37 to d30 d27 to d20 d17 to d10 d07 to d00 y402 y401 y400 y399 y398 y397 y6 y5 y4 y3 y2 y1 d57 to d50 d47 to d40 d37 to d30 d27 to d20 d17 to d10 d07 to d00
HD66350T 10 system overview figure 3 is a block diagram of the configuration of an xga (1024 768) compatible tft color panel with the HD66350Ts. the HD66350T latches 8-bit data for each dot, selects a level from the 256 positive-polarity or negative-polarity liquid-crystal application voltages generated internally, and outputs that voltage. by configuring pixels using r/g/b color filters, a full-color display of approximately 16,770,000 colors can be achieved. display data (8 bits x 6 pixels) HD66350T control signals (cl1, cl2, m, eio) liquid-crystal drive power supply (v9 to v0) counter-electrode voltage (v com ) HD66350T no.1 HD66350T no.2 HD66350T no.3 384 384 384 tft color panel 16,770,000 colors, 1024 x 768 dots rgb scan driver voltages (v gon , v goff ) controller scan driver 768 liquid-crystal drive power supply circuit scan driver control signals (frm, cl3) figure 3 system block diagram
HD66350T 11 123 1 1 512 512 123 23 cl1 cl2 eio 8-bit x 6-dot digital data one frame period frm cl1 hv256 (v0 to v4) odd pins even pins note: hv256 indicates 256 high-voltage grayscales. lv256 indicates 256 low-voltage grayscales. lv256 (v5 to v9) y1 y384 (y402) one horizontal period 768 lv256 lv256 hv256 hv256 lv256 lv256 hv256 hv256 hv256 hv256 lv256 lv256 figure 4 timing chart (example of a dot-inversion drive system)
HD66350T 12 operation timing cl2 eio1 d5j d4j d3j d2j d1j d0j pol1 pol2 cl1 eio2 (no. 1) eio2 (no. 8) y1 to y384 12 512 513 3 62 63 64 65 d3840 invalid d12 d6 d18 d366 d372 d378 d384 d390 d3822 d3828 d3834 d3840 invalid ic (no. 8) data latch period ic (no. 2) data latch period ic (no. 1) data latch period line when shl = v cc. 510 511 512 513 514 d3839 invalid d11 d5 d17 d365 d371 d377 d383 d389 d3821 d3827 d3833 d3839 invalid d3838 invalid d10 d4 d16 d364 d370 d376 d382 d388 d3820 d3826 d3832 d3838 invalid d3837 invalid d9 d3 d15 d363 d369 d375 d381 d387 d3819 d3825 d3831 d3837 invalid d3836 invalid d8 d2 d14 d362 d368 d374 d380 d386 d3818 d3824 d3830 d3836 invalid d3835 invalid d7 d1 d13 d361 d367 d373 d379 d385 d3817 d3823 d3829 d3835 invalid invalid invalid invalid invalid reset figure 5 operation timing the high level of the enable-input signal (when shl = v cc : eio1) is latched at the rising edge of the data-latch clock signal cl2, and data latching begins after one cl2 signal cycle. data of 8 bits rgb 2 pixels, i.e. 6 outputs, are simultaneously latched at the rising edge of the cl2 signal. at the rising edge of the 63rd clock pulse of the cl2 signal, the enable-output signal (when shl = v cc : eio2) is driven high, and the operation is automatically halted (the standby state is entered) when latching of data for 384 outputs is completed. by connecting the eio2 pin to the next-stage eio1 pin, the next- stage ic is activated in the same way. all the ic enable-output signals are reset at the rising edge of the cl1 signal. the data-latch clock signal cl2 does not require a clock-halted period. at least two clocks must be added to the necessary cl2 clocks (512 clocks for xga) in each horizontal period.
HD66350T 13 m signal and data input this example shows the relationship between the data input, m signal, and output level, with dot-by- dot inversion and frame inversion. the HD66350T driver must hold the m signal during the high-level period of cl1. the grayscale-voltage selection circuits for high and low voltages are operated according to the m signal level at the rise of cl1, and the grayscale voltages are output at the following rising edges of cl1. to provide stable output operation of the buffer amplifier, the output is placed in the high-impedance state in the high-level period of cl1. hv lv lv hv hv lv hv lv lv hv hv lv lv hv lv hv hv lv lv hv lv hv frame 2 frame 1 last-2 last-1 last 1 2 3 3 2 1 line cl1 m display data odd output pins even output pins high/low-voltage selection signal (internal) line 1 data line 1 data line 2 data line 3 data line 2 data line 3 data last line data last-1 line data note: hv indicates 256 high-voltage grayscales. lv indicates 256 low-voltage grayscales. figure 6 relationship between the m signal and data input
HD66350T 14 pin-by-pin inversion drive with regard to the inversion standard voltage for individual adjacent odd and even output pins, the HD66350T can generate 256-level positive-polarity and negative-polarity grayscale voltages. in addition, the liquid-crystal alternating-current drive can be controlled by switching the polarity of the m signal. (see the pin functions section.) in this way, when HD66350Ts are arranged on either the upper or lower side of a tft lcd panel, a dot inversion drive can be used in which grayscale voltages of different polarities are applied to individual adjacent dots by switching the m signal on each cl1 clock, reducing the crosstalk which adversely affects image quality, and thus achieving a high-quality display. odd frames hd66350 hd66350 gate driver even frames hd66350 hd66350 gate driver figure 7 dot inversion drive when the m signal switches on each cl1n clock, the following n-raster-row inversion drive can be used on each horizontal dot and vertical n-raster-row. odd frames hd66350 hd66350 gate driver even frames hd66350 hd66350 gate driver figure 8 n-raster-row inversion drive
HD66350T 15 when the m signal switches on each flm signal, the following frame inversion drive can be used on each horizontal dot and vertical frame. odd frames hd66350 hd66350 gate driver even frames hd66350 hd66350 gate driver figure 9 frame inversion drive
HD66350T 16 system application figure 10 shows system applications for xga-, sxga-, and uxga-sized tft color panels with the HD66350Ts. for the xga or sxga size, the dot clock frequency is halved by the timing converter and data are transferred to the drivers. for the uxga size, after the dot clock frequency is halved, data are transferred to odd and even drivers in parallel with the frequency halved again. since one horizontal period is shorter for the uxga size, the screen can be divided into upper and lower screens for the purpose of transferring data if the display panel has a large tft load capacitance. xga/sxga uxga 175mhz dclk 65/120 mhz 175 mhz 175 mhz 32.5/60 mhz dclk dclk dclk timing converter timing converter timing converter 44 mhz 44 mhz 44 mhz line memory odd/even parallel data transfer data transfer for upper and lower screen division frame memory 48 (8 bits x rgb x 2) 48 (8 bits x rgb x 2) 48 (8 bits x rgb x 2) 48 (8 bits x rgb x 2) 48 (8 bits x rgb x 2) figure 10 system applications
HD66350T 17 display data and output voltage with input of a 10-level liquid-crystal power supply and 8-bit digital data, the HD66350T outputs 256 grayscale voltage levels on the high-voltage side and 256 grayscale voltage levels on the low-voltage side. tables 2 and 3 show the relationship between the input voltages of the liquid-crystal power supply, digital codes, and output voltages. power supply circuit HD66350T v0 v9 y1 y402 256 positive- polarity levels dynamic range: max. 15.3 v 256 negative- polarity levels display data (8-bit digital data) figure 11 selection of the lcd drive output level
HD66350T 18 ladder resistance values (reference values) resistance name resistance value v0,v9 r0 600 r1 516 r2 450 r3 390 r4 339 r5 300 r6 270 r7 255 v1,v8 r8 240 r9 240 r10 240 r11 240 r12 243 r13 252 r14 261 r15 264 v2,v7 r16 270 r17 285 r18 300 r19 315 r20 330 r21 354 r22 366 r23 390 v3,v6 r24 420 r25 480 r26 540 r27 600 r28 660 r29 720 r30 900 r31 1200 v4,v5 total 13230 v0 v1 r0 r1 r2 r7 r8 r9 r31 v4 v2 v3 v5 v6 v7 v8 v9 r31 r9 r8 r2 r1 r0 r7 separate figure 12 ladder resistance
HD66350T 19 table 2 256 positive-polarity grayscale levels di5 di4 di3 di2 di1 di0 v0 v0-(v0-v1)x600/3120 v 0 -(v 0 -v 1 )x1116/3120 di7 di6 0 0 000 0000 0 000 0001 0 000 0010 0 000 0011 0 000 0100 0 000 0101 0 000 0110 0 000 0111 0 000 1000 1 000 0000 0 001 0000 0 001 1000 0 010 0000 0 010 1000 0 011 0000 0 011 1000 0 100 0000 0 100 1000 0 101 0000 0 101 1000 0 110 0000 0 110 1000 0 111 0000 0 111 1000 0h 01h 02h 03h 04h 05h 06h 07h 08h 10h 18h v 0 -(v 0 -v 1 )x1566/3120 v 0 -(v 0 -v 1 )x1956/3120 20h v 0 -(v 0 -v 1 )x2295/3120 28h v 0 -(v 0 -v 1 )x2595/3120 30h v 0 -(v 0 -v 1 )x2865/3120 38h v1 40h v 1 -(v 1 -v 2 )x240/1980 48h v 1 -(v 1 -v 2 )x480/1980 50h v 1 -(v 1 -v 2 )x720/1980 58h v 1 -(v 1 -v 2 )x960/1980 60h v 1 -(v 1 -v 2 )x1203/1980 68h v 1 -(v 1 -v 2 )x1455/1980 70h v 1 -(v 1 -v 2 )x1716/1980 78h v2 80h display data 256 positive-polarity grayscale levels code divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels
HD66350T 20 table 2 256 positive-polarity grayscale levels (cont) di5 di4 di3 di2 di1 di0 v2 v 2 -(v 2 -v 3 )x270/2610 v 2 -(v 2 -v 3 )x555/2610 di7 di6 80h f9 h fa h fb h fc h fd h fe h 88h 90h 98h v 2 -(v 2 -v 3 )x855/2610 v 2 -(v 2 -v 3 )x1170/2610 a0h v 2 -(v 2 -v 3 )x1500/2610 a8h v 2 -(v 2 -v 3 )x1854/2610 b0h v 2 -(v 2 -v 3 )x2220/2610 b8h v3 c0 h v 3 -(v 3 -v 4 )x420/5520 c8 h v 3 -(v 3 -v 4 )x900/5520 d0 h v 3 -(v 3 -v 4 )x1440/5520 d8 h v 3 -(v 3 -v 4 )x2040/5520 e0h v 3 -(v 3 -v 4 )x2700/5520 e8h v 3 -(v 3 -v 4 )x3420/5520 f0 h v 3 -(v 3 -v 4 )x4320/5520 f8 h v4 ff h v 4 + 1 / 8 x (v 3 -v 4 )x1200/5520 display data 256 positive-polarity grayscale levels code 1 111 0000 1 111 1000 1 111 1001 1 111 1010 1 111 1011 1 111 1100 1 111 1101 1 111 1110 1 111 1111 1 000 0000 1 000 1000 1 001 0000 1 001 1000 1 010 0000 1 010 1000 1 011 0000 1 011 1000 1 100 0000 1 100 1000 1 101 0000 1 101 1000 1 110 0000 1 110 1000 divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels
HD66350T 21 table 3 256 negative-polarity grayscale levels di5 di4 di3 di2 di1 di0 v9 v 9 -(v 9 -v 8 )x600/3120 v 9 -(v 9 -v 8 )x1116/3120 di7 di6 00h 01h 02h 03h 04h 05h 06h 07h 08h 10h 18h v 9 -(v 9 -v 8 )x1566/3120 v 9 -(v 9 -v 8 )x1956/3120 20h v 9 -(v 9 -v 8 )x2295/3120 28h v 9 -(v 9 -v 8 )x2595/3120 30h v 9 -(v 9 -v 8 )x2865/3120 38h v8 40h v 8 -(v 8 -v 7 )x240/1980 48h v 8 -(v 8 -v 7 )x480/1980 50h v 8 -(v 8 -v 7 )x720/1980 58h v 8 -(v 8 -v 7 )x960/1980 60h v 8 -(v 8 -v 7 )x1203/1980 68h v 8 -(v 8 -v 7 )x1455/1980 70h v 8 -(v 8 -v 7 )x1716/1980 78h v7 80h display data 256 negative-polarity grayscale levels code divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels 0 000 0000 0 000 0001 0 000 0010 0 000 0011 0 000 0100 0 000 0101 0 000 0110 0 000 0111 0 000 1000 1 000 0000 0 001 0000 0 001 1000 0 010 0000 0 010 1000 0 011 0000 0 011 1000 0 100 0000 0 100 1000 0 101 0000 0 101 1000 0 110 0000 0 110 1000 0 111 0000 0 111 1000
HD66350T 22 table 3 256 negative-polarity grayscale levels (cont) di5 di4 di3 di2 di1 di0 v7 v 7 -(v 7 -v 6 )x270/2610 v 7 -(v 7 -v 6 )x555/2610 di7 di6 80h f9 h fa h fb h fc h fd h fe h 88h 90h 98h v 7 -(v 7 -v 6 )x855/2610 v 7 -(v 7 -v 6 )x1170/2610 a0h v 7 -(v 7 -v 6 )x1500/2610 a8h v 7 -(v 7 -v 6 )x1854/2610 b0h v 7 -(v 7 -v 6 )x2220/2610 b8h v6 c0 h v 6 -(v 6 -v 5 )x420/5520 c8 h v 6 -(v 6 -v 5 )x900/5520 d0 h v 6 -(v 6 -v 5 )x1440/5520 d8 h v 6 -(v 6 -v 5 )x2040/5520 e0h v 6 -(v 6 -v 5 )x2700/5520 e8h v 6 -(v 6 -v 5 )x3420/5520 f0 h v 6 -(v 6 -v 5 )x4320/5520 f8 h v5 ff h v 5 + 1 / 8 x (v 6 -v 5 )x1200/5520 display data 256 negative-polarity grayscale levels code divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels divided into eight levels 1 111 0000 1 111 1000 1 111 1001 1 111 1010 1 111 1011 1 111 1100 1 111 1101 1 111 1110 1 111 1111 1 000 0000 1 000 1000 1 001 0000 1 001 1000 1 010 0000 1 010 1000 1 011 0000 1 011 1000 1 100 0000 1 100 1000 1 101 0000 1 101 1000 1 110 0000 1 110 1000
HD66350T 23 input data and output voltages the HD66350T outputs grayscale voltages of different polarities at the odd and even output pins with respect to the lcd counter-electrode voltage. as an example, figure 13 shows the relationship between the input data and output voltages when vlcd ?0.1 3 v0 3 v1 3 v2 3 v3 3 v4 3 vlcd/2 + 0.2, and vlcd/2 e 0.2 3 v5 3 v6 3 v7 3 v8 3 v9 3 0.1 v. 00000000 negative-polarity output 01000000 10000000 11000000 11111111 v0 v1 v2 v3 v4 vcom v5 v6 v7 v8 v9 lsb msb positive-polarity output input data the v4 and v5 levels are not output. figure 13 relationship between input data and output voltages
HD66350T 24 absolute maximum ratings item symbol ratings unit notes power supply voltage logic circuit (low voltage) v cc ?.3 to +5.0 v 1 lcd drive circuit (high voltage) v lcd ?.3 to +17 v 1 input voltage (high voltage) vt1 ?.3 to v lcd + 0.3 v 1, 2 input voltage (low voltage) vt2 ?.3 to v cc + 0.3 v 1, 3 storage temperature tstg ?5 to +110 c if the lsi is used beyond the above maximum ratings, it may be permanently damaged. it should always be used within its specified operating range for normal operation to prevent malfunction or degraded reliability. notes: 1. value when gnd = 0 v and agnd = 0 v. 2. applies to the cl1, cl2, shl, dxx, m, pol1, pol2, os, test, test2, stpls, fsl, and odd/evn input pins, and the eio1 and eio2 input/output pins when used as input. 3. specifies the voltage to be input to the lcd drive power supply pins. the following relationships must be observed: vlcd 3 v0 3 v1 3 v2 3 v3 3 v4 3 vlcd/2 + 0.2, and vlcd/2 ?0.2 3 v5 3 v6 3 v7 3 v8 3 v9 3 0. recommended operating ranges item symbol ratings unit notes power supply voltage logic circuit (low voltage) v cc +2.5 to +3.6 v 1 lcd drive circuit (high voltage) v lcd +10.0 to +15.5 v 1 g compensation power supply voltage (high voltage) vt1u v lcd /2 + 0.2 to v lcd v1 g compensation power supply voltage (low voltage) vt1l 0 to v lcd /2 ?0.2 v 1 driver output voltage vout 0.1 to v lcd ?0.1 v 1 max. clock frequency fmax 65 mhz operating temperature topr ?0 to +75 c note: 1. value when gnd = 0 v and agnd = 0 v.
HD66350T 25 electrical characteristics dc characteristics (conditions (unless otherwise specified): v cc ?gnd = 2.5 v to 3.6 v, v lcd ?gnd = 10.0 v to 15.5 v, ta = ?0 c to +75 c) item symbol applicable pin min. typ. max. uni t conditions note input high-level voltage (1) v ih1 cl1, shl, test, m, eio1(i), 0.8 v cc v cc v input low-level voltage (1) v il1 eio2(i), dij, pol1, pol2, os, and odd/evn 0 0.2 v cc v input high-level voltage (2) v ih2 cl2 0.8 v cc v cc v input low-level voltage (2) v il2 0 0.2 v cc v output high-level voltage v oh eio1(o) and eio2(o) v cc ?0.4 v i o h = 0. 4 ma output low-level voltage v ol 0.4 v i o l = 0. 4 ma input leakage current (1) il1 cl1,cl2,shl, test, dij, m, pol1, pol2, os, and odd/evn ? +5 m a input leakage current (2) il2 eio1(i) and eio2(i) ?0 +10 m a g compensation power supply voltage current iref v0, v5 1.0 2.0 ma v0?4 = 7 v v5?9 = 7 v v4, v9 ?.0 ?.0 ma output voltage deviation d v0 y1 to y402 3 8 mv input data 00 to ff 1 average output voltage dispersion d v d y1 to y402 10 mv input data 00 to ff 2 logic unit consumptive current i cc v cc 4 tbd ma v cc = 3.3 v v lcd = 15 v f cl1 = 83 khz 3 driver unit consumptive current i lcd v lcd 6 tbd ma (1 horizontal period = 12 m s) f c l 2 = 60 m hz input capacitance 1 c1 input pins except eio1 and eio2 5 10 pf ta = 25 c, vin = 0 v, f = 1 mhz input capacitance 2 c2 eio1 and eio2 10 20 pf
HD66350T 26 notes: 1. the output voltage deviation is the difference in adjacent output voltages for the same display data (within the chip). 2. the average output voltage dispersion is the difference in average output voltage between chips; the average output voltage is the average voltage within the chip for the same display data. the average output voltage dispersion is a reference value. 3. with outputs unloaded, and excluding the current flowing in v0?9. the specification applies to the display pattern (from among solid black, solid white, and dot check patterns) with the largest current.
HD66350T 27 ac characteristics (conditions (unless otherwise specified): v cc ?gnd = 3.0 v to 3.6 v, v lcd ?gnd = 10.0 v to 15.5 v, ta = ?0 c to +75 c, tr = tf = 2 ns) item symbol applicable pins min. typ. max. unit conditions notes clock cycle time trate cl2 15 ns clock low-level width tcwl cl2 5 ns clock high-level width tcwh cl2 5 ns data setup time tds dij and cl2 4 ns data hold time tdh dij and cl2 2 ns start pulse setup time tss eio1, eio2, and cl2 ? ns start pulse hold time tsh eio1, eio2, and cl2 7ns pol setup time tps pol1, pol2, and cl2 ? ns pol hold time tph pol1, pol2, and cl2 7ns cl1 high-level width tcl1wh cl1 3 m s data invalid period tinv cl1 and cl2 1 clk last data timing tldt cl1 and cl2 2 clk time between cl1 start pulses tcl1-eio cl1, eio1, and eio2 20 ns m setup time tms m and cl1 ? ns start pulse delay time tsd eio1, eio2, and cl2 15 28 ns cl = 25 pf driver output delay time (load condition) tdd cl1 and y1 to y402 6.0 9 m sv lcd = 15 v 95% write 1
HD66350T 28 note: 1. the specification applies to the following conditions. 60 pf 60 pf test point 1.3 k 1.3 k y1 to y384 5 stages figure 14 load conditions
HD66350T 29 switching characteristic waveforms the cl2 high-level width and low-level width are specified by vih = 0.8 v cc and vil = 0.2 v cc . other timings are specified by vih and vil = 0.5 v cc . tcwh tcwl trate tf tf 2 1 invalid invalid tsh cl2 dij, pol1 pol2 eio input of the first-stage ic (start pulse) cl2 cl2 cl1 m y1 to y402 y1 to y402 eio input of the first-stage ic (start pulse) eio input of the first-stage ic dxx 63 valid tdh tldt 641 64 tsd tdh tph tds tps 0.5v cc 0.5v cc 0.5v cc 0.5v cc 0.5v cc 0.5v cc 0.5v cc 0.5v cc 0.5v cc 0.5v cc 0.5v cc 0.5v cc 0.5v cc 0.5v cc 0.5v cc 0.5v cc 0.5v cc 0.8v cc 0.8v cc 0.8v cc 0.8v cc 0.2v cc 0.2v cc 0.2v cc 0.2v cc tss tsh 65 1 cl2 eio input of the next-stage ic 65 1 tss 66 2 64 invalid 642 643 tcl1wh tinv tcl1-eio tdd last output voltage x 5% last output voltage x 95% hi-z tdd tms 1 644 1 figure 15 switching characteristic waveforms
HD66350T 30 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:

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